SudeepJoshi22's repositories
Minor-Project-2023-RISC-V-processor
Verilog HDL code and documentation for pipelined RISC-V processors designed as a minor project by a team of 4. Includes testbench files, documentation, and sample programs. Completed as part of our 6th semester coursework.
CORDIC_Unit
CORDIC Unit Design and Synthesis Using Verilog HDL and YOSYS
Language:Verilog000
DHRUT-V
5-Stage Pipelined Custom RISC-V core
Language:VerilogApache-2.0000
FFT_HARDWARE
FFT Hardware written in TL-Verilog.
Language:Verilog000
Qm.n-and-Integer-Interconversions
Signed Integer to Qm.n binary conversion and vice versa written in Python.
Language:Python000
Language:C000
SudeepJoshi22
Config files for my GitHub profile.
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