Stefan's repositories
riscv_asconp_accelerator
Meta repo, Ascon-p instruction for RISC-V
riscv_asconp_accelerator_core
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
riscv_asconp_accelerator_isa_sim
Spike, a RISC-V ISA Simulator
riscv_asconp_accelerator_software
Ascon implementation utilizing the Ascon-p instruction for RISC-V
vivado-lxc
Launch an Ubuntu lxc container and install Xilinx Vitis/Vivado
ariane-sdk
Ariane SDK containing RISC-V tools and Buildroot
Language:Makefile000
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Language:SystemVerilogNOASSERTION000
edalize
An abstraction library for interfacing EDA tools
Language:PythonBSD-2-Clause000
vivado-docker
Dockerfile with Vivado for CI
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