This is the repository for the projects of Reti Logiche course held at Polimi.
The goal of the project is to develop a component for image equalization. The histogram equalization method of an image is a method designed to recalibrate the contrast of an image when the range of intensity values are very close by distributing them over the entire intensity range, in order to increase the contrast.
🛠️ All the projects were developed in VHDL using VIVADO tool.
The interface of the component is given and the implementation of the component is done as a state machine. An analysis about FPGA utilization and Time spent is done to verify if the component fulfill the implementation constraint
The repository contains :
- A folder with some test benches is present.
- The code of the component
- A pdf with the specification of the project
- A final report in which all the phases of the project are described in detail
🌐 The project needed to be written in Italian, so all the pdf files and comments are in Italian.
✔️ Final Evaluation: 30/30