Stanford AHA! Agile Hardware Center

Stanford AHA! Agile Hardware Center's repositories

garnet

Next generation CGRA generator

Language:PythonBSD-3-Clause109 12 181

Halide-to-Hardware

Language:C++NOASSERTION81 22 56

aha

Language:Python55021

AhaM3SoC

SoC Based on ARM Cortex-M3

Language:VerilogApache-2.027 23 1

lake

Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory macros.

Language:PythonBSD-3-Clause21 21 15

CGRAFlowDoc

Documentation for the entire CGRAFlow

19 170

doc

Papers, Posters, Presentations, Documentation...

18 14 1

lassen

The PE for the second generation CGRA (garnet).

Language:Python17 19 61

CGRAFlow

Integration test for entire CGRA flow

Language:C++BSD-3-Clause12 4 38

gemstone

Language:Python10 3 3

PowerDomainDesign

Language:Verilog7 200

canal

Language:Python6 180

CGRAMapper

CoreIR based mapping tool for CGRA

Language:C++BSD-3-Clause6 4 28

onyx

Language:TclBSD-3-Clause4 230

Applications

The applications for the Stanford AHA CGRA

Language:C++3 180

GarnetFlow

Language:Shell3 1 2

chipyard

Pre-release starter template for custom Chisel projects

Language:CNOASSERTION2 10

Primitives

Official Repo for keeping track of and defining all primitives.

BSD-3-Clause2 13 3

aha-flow-app

Language:JavaScript1 1 2

aha_tutorial

Aha Tutorial

Language:SCSS1 240

amber-vde

Language:Tcl1 200

Configuration

Language:SystemVerilogBSD-3-Clause1 220

hammer_implementation_flow

Language:Python1 210

aha-wiki-page

030

amber_demo

JTAG/Python/M3 code for Amber demo

0240

archipelago

000

clockwork

A polyhedral compiler for hardware accelerators

Language:C++000

delta

Language:Python010

GenClockTrials

Design with Generated Clocks

Language:Tcl0190

pdq

Language:Python019 1