Siudya / ORB_FPGA

Siudya/ORB_FPGA Issues

Final design is overutilizing the resources when rebuilding
Closed 5 months ago1
Change input image size
Updated a year ago3
NO TOP Module
Closed a year ago1
The descriptor calculated by Pynq is different from software_test
Closed a year ago9
Generating the bitstream
Closed a year ago1
Does the code here support NPC >1?
Closed a year ago2
More resources are used when project is rebuilt and synthesised
Closed a year ago11