SinnLiu

CPU_Design_MIPS

《CPU设计实战》学习记录及代码

2022HWC

A-convolution-kernel-implemented-by-Vivado-HLS

This project implements a convolution kernel based on vivado HLS on zcu104

hls4ml

Machine learning on FPGAs using HLS

MAERI_bsv

MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)

MAERI_bsv_isca2018

MAERI public release

maestro

An analytical cost model evaluating DNN mappings (dataflows and tiling).

NPU-on-Vivado-HLS

A NPU designed by Vivado HLS

SiamR-CNN

Siam R-CNN two-stage re-detector for visual object tracking

SkyNet

iSmart3 https://github.com/TomG008/SkyNet

ThunderGP

HLS-based Graph Processing Framework on FPGAs

tinyTPU

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

AI-Chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

AiLearning

AiLearning: 机器学习 - MachineLearning - ML、深度学习 - DeepLearning - DL、自然语言处理 NLP

CPU-on-Vivado-HLS

A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS

datamining

Free-TPU

Free TPU for FPGA with Lenet, MobileNet, Squeezenet, Resnet, Inception V3, YOLO V3, and ICNet. Deep learning acceleration using Xilinx zynq (Zedboard or ZC702 ) or kintex-7 to solve image classification, detection, and segmentation problem.

gemm_hls

Scalable systolic array-based matrix-matrix multiplication implemented in Vivado HLS for Xilinx FPGAs.

ics-pa

Machine_Learning_Resources

:fish::fish::fish: 机器学习面试复习资源

QtMips

MIPS CPU emulator

qtrvsim

RISC-V CPU simulator for education purposes

resnet_fpga

UCSD CSE 237D Spring '20 Course Project

rethinking-network-pruning

Rethinking the Value of Network Pruning (Pytorch) (ICLR 2019)

SinnLiu

Config files for my GitHub profile.

sinnliu.github.io

spooNN

FPGA-based neural network inference project with an end-to-end approach (from training to implementation to deployment)

xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.

YOLOv3-model-pruning

在 oxford hand 数据集上对 YOLOv3 做模型剪枝（network slimming）