Arjan Bink's repositories
core-v-cores
CORE-V Family of RISC-V Cores
core-v-docs
Documentation for the OpenHW Group's set of CORE-V RISC-V cores
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
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cv32e40p
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Language:SystemVerilogNOASSERTION000
cv32e40s
4 stage, in-order, secure RISC-V core based on the CV32E40P
Language:SystemVerilogNOASSERTION000
cv32e40x
4 stage, in-order, compute RISC-V core based on the CV32E40P
Language:SystemVerilogNOASSERTION000
fpnew
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
Language:SystemVerilogNOASSERTION000
ibex
Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.
Language:SystemVerilogApache-2.0000
obi
Repository that maintain the OpenBus Interface spec
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riscv-dbg
RISC-V Debug Support for our PULP Cores
Language:SystemVerilogNOASSERTION000
riscv-isa-manual
RISC-V Instruction Set Manual