Signal-Li / maskplace

code for paper "MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning"

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MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning

A new chip placement method based on visual representation learning.

Publication

Lai, Yao, Yao Mu, and Ping Luo. "Maskplace: Fast chip placement via reinforced visual representation learning." Advances in Neural Information Processing Systems 35 (2022): 24019-24030. (NeurIPS 2022, spotlight)

paper

Usage

You can start easily by using the following script.

cd maskplace
python PPO2.py

Parameter

  • gamma Decay factor.
  • seed Random seed.
  • disable_tqdm Whether to disable the progress bar.
  • lr Learning rate.
  • log-interval Interval between training status logs.
  • pnm Number of place modules for each placement trajectory.
  • benchmark Circuit benchmark.
  • soft_coefficient Whether to constriant the actions based on the wiremask.
  • batch_size Batch size.
  • is_test Testing mode based on the trained agent.
  • save_fig Whether to save placement figures.

Benchmark

The repo has provided the benchmark adaptec1 and ariane. For other benchmarks, you can download them by the following the link:

http://www.cerc.utexas.edu/~zixuan/ispd2005dp.tar.xz

Dependency

Citation

If you find our paper/code useful in your research, please cite

@article{lai2022maskplace,
  title={Maskplace: Fast chip placement via reinforced visual representation learning},
  author={Lai, Yao and Mu, Yao and Luo, Ping},
  journal={Advances in Neural Information Processing Systems},
  volume={35},
  pages={24019--24030},
  year={2022}
}

The placement process animation

Benchmark: Bigblue3

Placement Pos Mask t Wire Mask t
View Mask Pos Mask t+1 Wire Mask t+1

Standard Cell Placement

Fix macros and use DREAMPlace (classic optimization-based method) to place standard cells.

adaptec2 adaptec4 bigblue3

Full Benchmark demonstration

Benchmark DREAMPlace Graph DeepPR MaskPlace
adaptec1
HPWL (105) 17.94 26.05 21.36 6.57
Wirel (105) 19.24 28.54 25.64 7.36
Overlap 0.34% 1.89% 32.03% 0
adaptec2
HPWL (105) 135.32 359.35 197.13 79.98
Wirel (105) 140.91 381.64 205.78 83.59
Overlap 0.16% 1.54% 49.10% 0
adaptec3
HPWL (105) 112.28 392.66 340.29 79.33
Wirel (105) 119.23 409.37 372.02 85.28
Overlap 0 1.26% 29.10% 0
adaptec4
HPWL (105) 37.77 152.89 243.12 75.75
Wirel (105) 47.90 179.43 290.14 88.87
Overlap 0 7.43% 19.29% 0
bigblue1
HPWL (105) 2.50 8.32 20.49 2.42
Wirel (105) 3.41 10.00 25.68 3.14
Overlap 0 2.48% 9.33% 0
bigblue3
HPWL (105) 104.05 345.49 439.09 82.61
Wirel (105) 107.58 373.33 517.86 88.51
Overlap 8.06% 0.80% 85.23% 0
ariane
HPWL (105) 20.30 16.83 51.43 14.86
Wirel (105) 21.72 18.48 55.85 15.80
Overlap 0.78% 3.72% 38.91% 1.94%

About

code for paper "MaskPlace: Fast Chip Placement via Reinforced Visual Representation Learning"


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