Siddesh Patil's repositories
OpenROAD-flow-scripts
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
8-bit-ALU-in-verilog
8-bit ALU in Verilog.
Language:HTML000
anycore-riscv-src
The RTL source for AnyCore RISC-V
Language:SystemVerilogNOASSERTION000
CMOS-NOR-Gate_IITH-Hackathon
CMOS Implemented NOR Gate is designed using Synopsys custom design tools.
000
Complete-Python-3-Bootcamp
Course Files for Complete Python 3 Bootcamp Course on Udemy
Language:Jupyter Notebook000
embedded-systems-study-group_fork
Notes and Assignments of embedded systems study group
Language:RubyMIT000
eSim
This repository contain source code for new flow of FreeEDA now know as eSim
Language:PythonGPL-3.0000
platformio-projects
Arduino-powered projects built using PlatformIO IDE extension in Visual Studio Code
Apache-2.0000
sra-board-hardware-design
ESP32-based Development Board for Robotics and Embedded Applications
MIT000
walle_testing
Testing Walle
MIT000