This project involves high-level synthesis (HLS) of machine learning models for implementation on FPGAs. The objective is to convert the model to C using Keras2C perform HLS using Vivado HLS, and compare results with the results obtained through HLS4ml. Link for Model - https://github.com/Sai-004/MNIST-Digit-Classification-Model
- From the given model, we have generated RTL using hls4ml, through some modifications to the code generated by the hls4ml (as the code itself was not synthesisable). This RTL's performace in terms of latency and area was calculated.
- The given model is converted into c using keras2c.
- This c code is made hls-synthesisable.
- The performance of the obtained RTL was found through vivado-hls c-synthesis and RTL co-simulation.
- The c-code was modified using various techniques such as code-motion, hls pragmas addition and we have achieved latency just slightly higher than latency achieved through hls4ml.
- To view the HLS4ML Report,
cd ./hls4ML/hls4ml_model/myproject_prj/solution1/syn/report/myproject_csynth.rpt
- Baddigam Siddardhareddy, 210101027
- Nitish Kumar Pinneti, 210101125
- Naladala Navadeep, 210101072
- Munagala Devi Naga Sai Srinivas, 210101070
- Mukka Koushik, 210101069