Shakthi079's repositories
basic_verilog
Must-have verilog systemverilog modules
iic_uvm_tb
I2C testbench using the UVM
my-systemverilog-examples
A place to keep my synthesizable SystemVerilog code snippets and examples.
2D-convolution-Simulation
2D convolution module to perform convolution operation between a matrix and kernel
32-Bit-Floating-Point-Adder
Verilog Implementation of 32-bit Floating Point Adder
AXI
VIP for AXI Protocol
core-v-verif
Functional verification project for the CORE-V family of RISC-V cores.
Design-verification
UVM and Systemverilog based test benches for functional verification of a RAM module
easyUVM
A simple UVM example with DPI
formal_hw_verification
Trying to verify Verilog/VHDL designs with formal methods and tools
fourier-transmitter
A variable FPGA-based QAM transmitter with scalable mixed time and frequency domain signal processing.
FPGA-ftdi245fifo
FPGA-based USB fast communication using FT232H/FT600 chip.
INT_FP_MAC
INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
libgcrypt
GNU Crypto library
riscv-dv
SV/UVM based instruction generator for RISC-V processor verification
SoC-Design-DDR3-Controller
DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
SystemVerilog-Implementation-of-DDR3-Controller
The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a predefined DDR3 memory. Successful design verification is achieved via a specialized test bench and connected to provided AHB by a SystemVerilog interface.
uvm-basics
my UVM training projects
uvm_course_cadence
Labs for UVM in Cadence Xcelium
UVM_TestBench_For_Ring_Counter
Complete UVM TestBench For Verification Of Ring (Onehot) Counter
verilog-axis
Verilog AXI stream components for FPGA implementation
verilog-dsp
Verilog digital signal processing components