Scuzz3y / 2019-ectf-hardware

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2019 MITRE Collegiate eCTF hardware Base Design

Created for Vivado 2017.4

This project is a modification to the project found at https://github.com/Digilent/Arty-Z7-10-base-linux.

Getting Started

Download the Arty-Z7-10 board files and install them into your Vivado installation path:

git clone https://github.com/Digilent/vivado-boards
cp -r vivado-boards/new/board_files/arty-z7-10/ /opt/Xilinx/Vivado/2017.4/data/boards/board_files/

Open Vivado and source the provided create_project.tcl file in the TCL console to generate the Vivado Project.

In the TCL Console:

git clone https://github.com/mitre-cyber-academy/2019-ectf-hardware.git
cd 2019-ectf-hardware/proj/
source create_project.tcl

This will generate and open the base design.

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Language:VHDL 74.8%Language:Verilog 17.1%Language:SystemVerilog 4.0%Language:HTML 2.8%Language:C 1.1%Language:Tcl 0.1%Language:Coq 0.0%Language:Shell 0.0%Language:Batchfile 0.0%