Sargastico / Neko-V

RISC-V 32-bit FPGA [Verilog] Processor

Neko-V

RISC-V 32-bit FPGA [Verilog] Processor with neko ears! :p
For study purposes (sh1TTy Code Disclaimer)

Implements the RV32E ISA (Instruction Set Architecture).

# Requirements:

• GTKWave
• Icarus Verilog

# Running tests

Running a test from a specific module, ALU for example:

Path : /Neko-V/cpu/alu

iverilog -o alu_tb.vvp alu_tb.v

To generate the wave view:

vvp alu_tb.vvp

The output should not contain any errors. Open the file with the GTKWave:

gtkwave alu_tb.vcd

Result:

To test the CPU module, it's necessary to specify the path for all other modules:

iverilog -o cpu_tb.vvp cpu_tb.v -I ./cpu/programCounter -I ./cpu/registerBank -I ./cpu/instructionDecoder -I ./cpu/alu

Then:

vvp cpu_tb.vvp

# Compile the test code

To compile the assembly instructions from 'test' folder, install the gcc for riscv (for ubuntu):

sudo apt install gcc-10-riscv64-linux-gnu

Generate .hex code for the online simulator:

make simhex

Generate .mem for the CPU unit testing:

make testmem

Clean the test files:

make clean

# Greetz & References:

Awesome RISC-V projects:

• "Riscow" by racerxdl
• "DarkRISCV" by Darklife

Recommended Reading:

• "The RISC-V Reader: An Open Architecture Atlas"