A Simulative CPU Running on MIPS32 System Based on Logisim, including the memory register group RegFile, the operator ALU, the controller Control.
A MIPS register group with 32 32-bit registers inside.
- Circuit Diagram: Regfile.png
- Logisim File: Regfile.circ
A 32-bit arithmetic unit that supports 13 operations.
- Circuit Diagram: ALU.png
- Logisim File: ALU.circ
The new instruction will execute after the last instruction finished the parts in the pipeline.
- Circuit Diagram: SingleCycleCPU.png
- Logisim File: SingleCycleCPU.circ
Divide the pipeline into 5 segments and suppose there is no conflict between instructions.
- Circuit Diagram: IdealPipelineCPU.png
- Logisim File: IdealPipelineCPU.circ
Used Bubble Insertion method to prevent data and control hazard.
- Circuit Diagram: BubblePipelineCPU.png
- Logisim File: BubblePipelineCPU.circ
Used Data Redirection method to prevent data hazard, optimized so that it runs less cycles compared to Bubble Insertion method.
- Circuit Diagram: RedirectionPipelineCPU.png
- Logisim File: RedirectionPipelineCPU.circ
A multiple cycle CPU supporting Interruption processing.
- Circuit Diagram: InterruptCPU.png
- Logisim File: InterruptCPU.circ
There are various programs for testing the CPU in the Benchmarks folder, with a combined final benchmark named Benchmark.hex.
All the benchmarks are assembled by Mars.jar, a powerful MIPS assembling and debugging tool.
- Logisim, an educational software for digital circuit simulation.
- Mars, a lightweight IDE for MIPS compiling and running system.