SanKing-Lee

JavaAdvancedProgramDesign

2021HWAutoGrader

2021华为软件精英挑战赛 程序输出分析器

AcceleratedLeNet

AlgorithmsAndDataStructures

AndroidComment

cdma_training

cdma_training

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

CompilerByJava

CompilerInC

CQUThesis

:pencil: 重庆大学毕业论文LaTeX模板---LaTeX Thesis Template for Chongqing University

EasySign

ElfReader

FileManager

FPGA-Design-Experiment

java-design-patterns

Design patterns implemented in Java

JavaTools

jvmGo

leetcode

linux-xlnx

The official Linux kernel from Xilinx

MobileNet-in-FPGA

Generator of verilog description for FPGA MobileNet implementation

nowcoder

OperatingSystemsThreeEasyPieces

PyWaveCompare

step_into_mips

一步一步写MIPS CPU

StudentCourseSystem

tablesaw

Java dataframe and visualization library

uvm-generator

UVM Auto Generate ; Verify Project Build; Verilog Instance

Vitis-AI

Vitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.

vivado_sample_design