Safeer Hyder's repositories
Digital-System-Design
This repository manages DSD lab code files.
FPGA_Ultrasound_DAS_Beamformer
This repository contains codes and texts related with the FPGA RTL Implementation of the Delay and Sum Beamformer
DeepUltrasound
Deep Learning RF Interpolation for Compressive Ultrasound Imaging
covid-chestxray-dataset
We are building an open database of COVID-19 cases with chest X-ray or CT images.
deeplearningLDCT
Deep Learning Low-Dose CT Project: AAPM-Net, WavResNet
Final-Year-Project
This repository contains the details of my Final Year Project. and the topic for my FYP is Improvements in Medical Ultrasound Beamforming Quality using Deep Learning.
Fixed-Floating-Point-Adder-Multiplier
16-bit Adder Multiplier hardware on Digilent Basys 3
FPGA-Design-Flow-using-Vivado
This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
High-Level-Synthesis-Flow-on-Zynq-using-Vivado-HLS
This course provides professors with an understanding of high-level synthesis design methodologies necessary to develop digital systems using Vivado HLS. Now under 2018.2 version.
Interfacing-TDS-Sensor-with-Arduino
The TDS Sensor is interfaced with microcontroller Arduino to get the TDS value of water to check its quality
Pmod
Collection of simple interfaces for Digilent Pmods
PYNQ_Bootcamp
PYNQ Bootcamp 2019 teaching materials.
SAFEERHYDER
Config files for my GitHub profile.
Verilog-Utilty-Modules
Collection of Verilog utility modules
Zynq-Design-using-Vivado
This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.