RustamC

OpenLane

** README **: OpenLane+DREAMPlace (PL_DREAMPLACE_GLB_PLACEMENT in config.json) option for global placement in fpi branch

circuit_training

circuit_training_openlane

Instructions on how to run Circuit Training in OpenLane flow

transistor_counter

Simple transistor counter in Verilog gate-level netlist using data from CDL

DQN_GlobalRouting

Applying Deep Q-learning for Global Routing

DREAMPlace

Deep learning toolkit-enabled VLSI placement

DREAMPlaceFPGA

An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit

MacroPlacement

*** README ***: for convertors checkout this branch: pb2def

netlist

generic NetList data structure for VLSI

rsta

Rust bindings for OpenSTA

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

wotan

A tool for early-stage FPGA routing architecture evaluation using analytic and heuristic methods (and no benchmarks).

yosys

Yosys Open SYnthesis Suite

toolchain-iverilog

:seedling: Icarus Verilog pre-built binaries: GNU/Linux(+ARM), Windows and Mac OS