Ruiggg / Design-of-dual-port-SRAM-

Design-of-dual-port-SRAM-

Figure 1. True Dual-Port RAM with a Single Clock Top-Level Diagram

Table 1. True Dual-Port RAM with a Single Clock Port Listing

1. Port-Name-------------------Type-----Description
2. dataa[7:0], datab[7:0]------Input----8 bit data inputs of port A and port B
3. addr_a[5:0],addr_b[5:0]-----Input----6 bit address inputs of port A and port B
4. we_a, we_b------------------Input----Write enable inputs of port A and port B
5. clk-------------------------Input----Clock input
6. q_a[7:0], q_b[7:0]----------Output---8 bit data outputs of port A and port B