Design Compiler Synthesis Error
cr8601 opened this issue · comments
Hi,
I am trying to run a simple synthesis with Synopsis Design Compiler and ending up in an error:
rtl/verilog/core/plic_dynamic_registers.sv:607: symbol register_function must be a constant or parameter. (VER-260)
Has this ever been tested with Design Compiler?
Best regards
cr8601
Honestly I don’t know if this was tried with Design Compiler.
Can you point me to the error? This might be a case of just asking the question differently (i.e. rewriting RTL).
The ‘ dynamic_registers’ block is quite compiler heavy
Richard
Richard Herveille
Managing Director
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***@***.***
On 16/06/2021, 11:15, "cr8601" ***@***.***> wrote:
Hi,
I am trying to run a simple synthesis with Synopsis Design Compiler and ending up in an error:
rtl/verilog/core/plic_dynamic_registers.sv:607: symbol register_function must be a constant or parameter. (VER-260)
Has this ever been tested with Design Compiler?
Best regards
cr8601
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The problematic verilog is the case statement:
plic_dynamic_registers.sv#L607
register_function(r) is a function, but needs to be constant or parameter for synthesizable (system)-verilog
The function is declared here:
plic_dynamic_registers.sv#L211