RoaLogic / ahb3lite_apb_bridge

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

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DC compiler incorrectly synthesises ahb to apb bridge

FireFox317 opened this issue · comments

First of all thanks for this IP, I'm using it in a research project on the University of Twente in the Netherlands.

However in commit 18d9aee you introduced resetting some state to 'X's. When using the DC compiler in optimizing mode (compile_ultra) this generates logic that is incorrect. I'm not sure if this is a bug in the DC compiler or not, but my issue was fixed by changing the x's in the file to 0's.

It's even worse that this was not caught by formality.

To be clear when doing a post-synthesis simulation it would end up in a undefined (x's) state when trying to convert an ahb to apb transaction.

Hi Richard,

Yes, I did run formality on the RTL vs the netlist and it was succesful, this was however with the IP integrated into a bigger system. I will do it on this IP soon, don't have time for that now. I'm not sure if DC compiler treats not resetting versus resetting to x's the same tho.

I did notice that when a transaction started, the lower bits of apb_beat_cnt were only initialized, the higher bits stayed as x's. My guess is that DC compiler can optimized some logic regarding the apb_beats function, but i'm not completely sure.

Regards,
Timon