Altera virtual JTAG interface

[lapnd]

Hi,
As in the project status: "Core is up and running, happily debugging RISC-V. Tested in HW on an Altera development board (using the Altera virtual JTAG interface)"
Do you have link/few notes... on how to try this with Altera board?
I would like to try with DE10Lite board where only single USB cable can be used as programming interface as well as debugging the app run on the core.

[rherveille]

If you specify Altera for Technology, then the virtual JTAG port will be instantiated. VirtualJTAG uses USER0 and USER1 registers to implement VIR (Virtual Instruction) and VDR (Virtual Data) registers. It enables user modules to use the device JTAG port Richard Richard Herveille Managing Director Phone [phone] Cell [phone] ***@***.*** On 25/12/2021, 17:19, "lapnd" ***@***.***> wrote: Hi, As in the project status: "Core is up and running, happily debugging RISC-V. Tested in HW on an Altera development board (using the Altera virtual JTAG interface)" Do you have link/few notes... on how to try this with Altera board? I would like to try with DE10Lite board where only single USB cable can be used as programming interface as well as debugging the app run on the core. — Reply to this email directly, view it on GitHub, or unsubscribe. Triage notifications on the go with GitHub Mobile for iOS or Android. You are receiving this because you are subscribed to this thread.Message ID: ***@***.***>