This repository showcases my work during the course RISC-V Based MYTH during a (very intense) week in September 2023.
To red the full documentation and see all the steps and code, please head to:
- Day 1-2, for some basis on compiling, simulating and debugging
- Day 3-4-5, for the TL-Verilog implementation of the calculator (day 3) and the pipelined RISC-V CPU architecture (day 4-5).
Enjoy and please feel free to contact me via issues :)