ReactorScram / rust-circuit-sim

A digital logic sim in Rust

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A crude digital logic sim in Rust.

See functions test_half_adder and test_full_adder for example usage.

A World represents a simulation. A World has Wires, which can have propagation 
delay, Gates which can perform logical operations, Junctions which hold a 
voltage Level, Signals which represent currently-propagating signals, and Time 
which is the current simulated time.

Stepping the world advances the simulation time by the minimum amount of time
required for at least one Signal to propagate to its destination.

The simulated time is a 64-bit integer. Because there is no floating-point 
rounding, the simulation should be deterministic across platforms.

A Junction is a point in the circuit that has a voltage. Junctions have no 
other state.

A Wire connects two Junctions directionally. Connecting Wires in a loop results
in undefined behavior. A single Wire has no fan-in or fan-out. Multiple wires 
may fan out from a junction, but multiple wires with the same output junction 
may have undefined behavior. Each Wire has a delay factor. When a signal enters 
a Wire, the signal is stored in World::delays until the delay has passed, at 
which point it instantly appears at the output junction of the Wire.

A Gate connects one or more input junctions to one output junction. Gates
currently have no internal state and no delay factor. When a signal reaches a 
Gate, the result is computed and transmitted to the output instantly.

Update for October 8th:

I refactored a lot so that it would be possible to programatically assemble an
array of full adders into a single ripple adder circuit. I tested it with 8
full adders, and added 19 + 93 = 112. The new top-level function is 
test_ripple_adder. The assembling process needs more work, right now it would 
be very difficult to do it for anything more complex than a ripple adder.

TODO:

* Use an online insertion sort to keep the delays vec sorted, instead of
  doing a full sort every time.
* Use a hash map from junctions to gates to avoid scanning every gate 
  on every frame.
* Add stateful gates such as flip-flops.
* Add gates with multiple outputs, such as adders.
* Test with bigger and bigger circuits.

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A digital logic sim in Rust

License:GNU Affero General Public License v3.0


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