Qu Yuwei (Rad1anceX)

Rad1anceX

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Company:Fudan University

Location:Shanghai

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d2l-zh

《动手学深度学习》:面向中文读者、能运行、可讨论。中英文版被70多个国家的500多所大学用于教学。

Language:PythonLicense:Apache-2.0Stargazers:60849Issues:1053Issues:0

LaTeX-OCR

pix2tex: Using a ViT to convert images of equations into LaTeX code.

Language:PythonLicense:MITStargazers:11645Issues:71Issues:265

dive-into-llms

《动手学大模型Dive into LLMs》系列编程实践教程

matmulfreellm

Implementation for MatMul-free LM.

Language:PythonLicense:Apache-2.0Stargazers:2838Issues:44Issues:29

Vitis-Tutorials

Vitis In-Depth Tutorials

vscode-terosHDL

VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!

Language:JavaScriptLicense:GPL-3.0Stargazers:530Issues:22Issues:438

ventus-gpgpu

GPGPU processor supporting RISCV-V extension, developed with Chisel HDL

Language:ScalaLicense:MulanPSL-2.0Stargazers:523Issues:13Issues:25

llm-autoeval

Automatically evaluate your LLMs in Google Colab

Language:PythonLicense:MITStargazers:497Issues:7Issues:20

CoLLiE

Collaborative Training of Large Language Models in an Efficient Way

Language:PythonLicense:Apache-2.0Stargazers:401Issues:10Issues:69

verilog-eval

Verilog evaluation benchmark for large language model

Language:SystemVerilogLicense:NOASSERTIONStargazers:149Issues:8Issues:4

xictools

XicTools: Xic graphical editor, WRspice circuit simulator, and accessories. for electronic design.

act

ACT hardware description language and core tools.

Language:C++License:GPL-2.0Stargazers:96Issues:15Issues:24

HiSparse

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

Language:C++License:BSD-3-ClauseStargazers:76Issues:19Issues:2

ventus-gpgpu-verilog

GPGPU supporting RISCV-V, developed with verilog HDL

NaiveCircuitSimulator

A simple electric circuit simulator with pleasant GUI written in C++ using olc Pixel Game Engine.

Language:C++Stargazers:38Issues:2Issues:0

simple-AXI2AHB-bridge

AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

Language:VerilogStargazers:31Issues:0Issues:0

HeteroGen

HeteroGen: transpiling C to heterogeneous HLS code with automated test generation and program repair (ASPLOS 2022)

Language:PythonStargazers:16Issues:1Issues:0

CSGO-fpga-Edition

FPGA Verilog HDL design project (DE1-SoC)

Language:VerilogStargazers:12Issues:1Issues:0

FDRA

DRA+RISC-V Exploration Framework

Language:C++License:BSD-3-ClauseStargazers:12Issues:1Issues:3

FPGA_NN

A neural network built in Verilog for the DE1-SoC FPGA board for handwritten digit recognition.

Language:VerilogLicense:GPL-3.0Stargazers:11Issues:2Issues:0
Language:CLicense:NOASSERTIONStargazers:10Issues:2Issues:0

ASP-SoC.github.io

Audio Signal Processing SoC Project Website

Language:HTMLStargazers:6Issues:5Issues:0

CircuitSimulator_SFML

Circuit Simulator in C++/SFML

Language:C++License:Apache-2.0Stargazers:6Issues:1Issues:0

ECE243_Reversi

Final project for ECE243

Translaite

A language learning solution to learn vocabulary from day-to-day objects with front-end on De1-SoC Cyclone V FPGA and backend on a Raspberry Pi, incorporating Microsoft Azure Cognitive Services

Language:HTMLStargazers:3Issues:2Issues:0
Language:CLicense:MITStargazers:2Issues:0Issues:0

HMSpice

It is an electronic circuit simulator for purely resistive circuits based on "Circuit Simulation" book by Farid N. Najm, developed at Shiv Nadar University.

Language:C++License:NOASSERTIONStargazers:2Issues:1Issues:0

Whac-A-Mole-FPGA

A project by Verilog HDL to play the whac-a-mole game on BASYS 2 FPGA board.

Language:VerilogLicense:MITStargazers:2Issues:2Issues:0

De1-SoC-Verilog-Audio-HW-FX

A hardware-only audio implementation on the Altera DE1-SoC FPGA using the on-board Wolfson WM7831 codec and the 64MB SDRAM

Language:VerilogLicense:MITStargazers:1Issues:0Issues:0