RYZF-SUCC / FPGA_LeNet5_ws_8x8

FPGA implement of 8x8 weight stationary systolic array DNN accelerator

FPGA_LeNet5_ws_8x8

FPGA implement of 8x8 weight stationary systolic array DNN accelerator

FPGA implement of 8x8 weight stationary systolic array DNN accelerator

Language:Verilog 78.0%Language:C++ 20.0%Language:C 1.5%Language:Python 0.3%Language:Makefile 0.2%