RV-AT

NyuziProcessor

GPGPU microprocessor architecture

OpenFPGA

An Open-source FPGA IP Generator

EveIDE_LIGHT

A lightweight IDE that supports verilog simulation and Risc-V code compilation

vortex

alice5

SPIR-V fragment shader GPU core based on RISC-V

80x86

80186 compatible SystemVerilog CPU core and FPGA reference design

SoC_Automation

SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports AMBA AHB and APB.

HGA101_GPU

PVS32_SoC

Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus

PVS332

Pan's SoC Gen 2, multicycle RV32ia

PVS464

SM3_core

riscv-dv

SV/UVM based instruction generator for RISC-V processor verification

glide

3Dfx Glide -- forked from CVS repository at https://sourceforge.net/projects/glide/

uvm

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

core_usb_host

Basic USB 1.1 Host Controller for small FPGAs

EVE_IDE

flexpret

CacheSim

A simple cache simulator

UVMReference

Reference examples and short projects using UVM Methodology

tinygl

TinyGL : a Small, Free and Fast Subset of OpenGL*

gplgpu

GPL v3 2D/3D graphics engine in verilog

Atalanta

Atalanta is a modified ATPG (Automatic Test Pattern Generation) tool and fault simulator, orginally from VirginiaTech University.