RTimothyEdwards

R. Timothy Edwards's repositories

magic

Magic VLSI Layout Tool

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open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with setups for the SkyWater 130nm and Global Foundries 180nm open processes.

Language:PythonApache-2.0268 20 207

qflow

Qflow full end-to-end digital synthesis flow for ASIC designs

Language:C179 15 45

netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

Language:CNOASSERTION104 10 58

XCircuit

XCircuit circuit drawing and schematic capture tool

Language:CGPL-2.0103 10 15

qrouter

Qrouter detail router for digital ASIC designs

Language:CGPL-2.054 8 6

irsim

IRSIM switch-level simulator for digital circuits

Language:CGPL-2.031 5 6

capiche

Parasitic capacitance analysis of foundry metal stackups

Language:PythonGPL-2.01000

caravel_openframe_project

Example digital project for the Efabless Caravel "openframe" harness

Language:VerilogApache-2.07 1 15

tutorial_layout

Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.

Language:ShellApache-2.0700

sky130_ef_ip__opamp

Instrumentation amplifier (analog IP example)

Language:VerilogApache-2.0600

chipalooza_projects_1

Chipalooza challenge first test chip of projects

Language:MakefileApache-2.0500

sky130_ef_ip__cdac3v_12bit

12-bit capacitive DAC

Language:Makefile2 10

sky130_ef_ip__rdac3v_8bit

8-bit resistor ladder DAC with 3.3V output range

Language:MATLABApache-2.0200

sky130_ef_ip__samplehold

Analog 3.3V sample and hold circuit, with buffered output

Language:VerilogApache-2.0200

sky130_ef_ip__xtal_osc_32k

Low power, low speed (32.768kHz) crystal oscillator circuit for sky130 technology

Language:ShellApache-2.0200

Smoothieware

Modular, opensource, high performance G-code interpreter and CNC controller written in Object-Oriented C++

Language:C++2 20

contact_programmed_ROM_cells

Set of layouts for contact-programmed ROM values of various bit widths.

1 10

fracn_dll

Alternative version of the Caravel digital locked loop (DLL) with a fractional feedback divider

Language:Verilog100

sky130_ef_ip__biasgen

Current bias generator circuit for distributing bias currents to analog circuits.

Language:ShellApache-2.0100

sky130_ef_ip__ccomp3v

Continuous analog comparator, 1mV resolution

Language:VerilogApache-2.0100

sky130_ef_ip__rc_osc_16M

16MHz (nominal) current-starved ring oscillator

Language:ShellApache-2.0100

sky130_ef_ip__xtal_osc_16M

High speed (16MHz) crystal oscillator in sky130 technology

Language:ShellApache-2.01 10

tt-fpga-hdl-demo

TinyTapeout demo

Language:TL-VerilogApache-2.0100

sky130_ef_ip__analog_switches

Set of analog switch circuits for general-purpose use

Language:ShellApache-2.0000

FOSSi_workshop

Files related to FOSSi Latch-Up 2024 workshop, Sunday, April 21, 2024.

Language:ShellApache-2.0000

globalfoundries-pdk-libs-gf180mcu_fd_pr

Primitives for GF180MCU provided by GlobalFoundries.

Language:PythonApache-2.0000

sky130_ef_ip__rc_osc_500k

Medium-speed low-power oscillator (500kHz) with enable.

Language:ShellApache-2.0000

sky130_ef_ip__rheostat_8bit

8-bit programmable rheostat with 50kohm end-to-end resistance, in the sky130 process.

Language:MATLABApache-2.0000

skywater-pdk-libs-sky130_fd_io

IO and periphery cells for SKY130 provided by SkyWater.

Apache-2.0000