Chair of Electronic Design Automation's repositories
upec-boom-verification-suite
This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks based on the Unique Program Execution Checking (UPEC) approach.
RISCV-Core
5-stage RISC-V core (RV32IM) with pipelining designed for educational purposes by RPTU Kaiserslautern, Germany
SecureBOOM
Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)
VDSProject
This repository contains the basic files for the class project of the course "Verification of Digital Systems"
symbolic-pmp
This repository contains a symbolic and secure configuration template for the RISC-V Physical Memory Protection (PMP) to be used in SV/SVA based verification flows.
ADSProject
This repository contains the basic files for the class project of the course "Architecture of Digital Systems I"
OpenTitan_with_Access_Control
OpenTitan Silver Release v5 copy for security improvements
Security-Conscious-Hardware
Collection of experiments on data-oblivious hardware designs that dynamically adjust their latency
thesis-template
LaTeX template for Bachelor and Master theses at EIS chair
BOOMv3-delay-on-miss-dcache
The repository contains the source files for the BOOM v3, patched against transient execution attacks using UPEC iterative patch cycles.
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
rocket-chip-inclusive-cache
An RTL generator for a last-level shared inclusive TileLink cache controller
Speckle
A wrapper for the SPEC CPU2017 benchmark suite.