RISC-V International Open Source Laboratory's repositories
OpenRPDK28
Open source process design kit for 28nm open process
CyberRio-V1.0
A small RISC-V core written in synthesizable Verilog, with the majority of the Verilog code implementation done using GPT-4, that supports the RV32I unprivileged ISA and parts of the privileged ISA, namely M-mode.
GreenRio-V1.0
Open source RISC-V CPU
GreenRio-V2.0
Open source RISC-V CPU
OpenBMIChip
The OpenBMIChip is an incredible piece of silicon chip, specifically designed to support the incredibly fascinating Brain-Machine Interface (BMI).
OpenSTDCell28
Open stadard cell library for open 28nm process
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CXLandNUMA
Resource map of CXL, NUMA and UCIe
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OpenChatEDA
Large language model platform for EDA tool
GPL-2.0000
PicoRioCPU2641300
PicoRio2 CPU MPW
Language:VerilogApache-2.0000
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sail-riscv-rgen
Sail RISC-V model with RGen enhancements
NOASSERTION000