RAOUMERTC73 / -Design-and-Verification-Trainee

SemiRise Training Program: currently working on a remote training focused on Digital logic design, Verilog, System Verilog, Computer Architecture. This training has provided me with hands-on experience in designing and verifying digital circuits using advanced software tool.

WEEKS-OF-RTL

The git repo contain my training Semirise is leading by the professional working in IC design and Verification companies.In this training we learn Digital logic design, Verilog and System Verilog language for IC designing and Verification, C programming, Computer Architecture for processor designing and verification.In this training, I learned the Basic concept and implementation of different modules in the Verilog language which are followed as and this repo aslo a part of my course which I learned on line platform Mindluster and Udemy_Verilog_Comprehensive_Masterclass git practice repo and In my university course Digital Logic Design(DLD) and Advanced Digital Electronic and Interfacing Techniques (ADIT).

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Here is the list of weekly or daily updates RTL Codes:

ALL LOGIC GATES AND HALF ADDER.
FULL ADDER .
FULL SUBTRACTOR.
8x1 Mux (Three Modelling styles).
8x1 Mux by 4x1 mux and 2x1 mux.
GATES BY 2X1 MUX.
8x1 Demux .
1x8 Demux by 1x2 demux and 1x4 demux.
8:3 enocder .
3:8 decoder .
8:3 priority enocder (Bhevioural model).
BCD TO 7 SEGMENT.
COMPARATOR 4 BIT(Bhevioural model).
ADDER-SUBTRACTOR.
FLIPFLOPS (Behavioural model).
64 bit register.
Multiplier 4-Bit.
BARREL SHIFTER.
Counters.
Serial in Serial Out shift register(SISO).
Serial in parallel Out shift register.(SIPO)
parallel in parallel Out shift register.(PIPO)
parallel in Serial Out shift register.(PISO)
Universal Shift Register.
ALU 8-bit
Swapping of two numbers
N bit square number.
CLOCK DIVIDER.
DIGITAL CLOCK.
RAM.
FSM .
Synchronous FIFO.
LAST IN FIRST OUT (STACK).
DIGITAL CLOCK.
Simple processor Design key concept.
Processor implementation on Verilog / System Verilog language.