QuantamHD

lemon

LEMON stands for Library for Efficient Modeling and Optimization in Networks. It is a C++ template library providing efficient implementations of common data structures and algorithms with focus on combinatorial optimization tasks connected mainly with graphs and networks.

XDM

This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

bazel_rules_hdl

Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)

clang-tidy-review

Create a pull request review based on clang-tidy warnings

ethan-evan-random-numbers

Random Numbers

evan-submission

fancy-chip-inc

Fancy

gf180-testchip

globalfoundries-pdk-libs-gf180mcu_fd_sc_mcu7t5v0

7 track standard cells for GF180MCU provided by GlobalFoundries.

klayout

KLayout Main Sources

mpw_precheck

open-source-eda-birds-of-a-feather.github.io

open_pdks

PDK installer for open-source EDA tools and toolchains. Distributed with a setup for the Google/SkyWater 130nm process.

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

OpenSTA

OpenSTA engine

OpenSTA-parallax

platforms

Constraint values for specifying platforms and toolchains

rules_boost

bazel build rules to use boost in bazel projects

skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

skywater-pdk-libs-sky130_fd_pr_reram

subleq

https://caravel-user-project.readthedocs.io

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

swig

SWIG is a software development tool that connects programs written in C and C++ with a variety of high-level programming languages.

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

xls

XLS: Accelerated HW Synthesis

xo

XO monorepo

yosys

Yosys Open SYnthesis Suite

yosys-symbiflow-plugins

Plugins for Yosys developed as part of the SymbiFlow project.