QingmuDeng / MIPS_FPU

A MIPS single cycle CPU that supports IEEE-754 floating point addition and subtraction.

CompArch Lab 4: Addtional Features for a Single Cycle CPU

Daniel Connolly, Qingmu "Josh" Deng

Microproposal

For lab 4 we are aiming for the following enhancement to our single cycle CPU:

• Add multiplication functionality to integer operations(to be able to verify factorial code on our cpu)
• A exception handler (MIPS coprocessor 0) that is able to handle exceptions in normal integer operations
• A floating point unit (MIPS coprocessor 1) that is able to add, subtract, multiply and divide