QDucasse

nn_benchmark

🧠 Benchmark facility to train networks on different datasets for PyTorch/Brevitas

lectern

💡 Notes and bib manager (articles are mostly related to language virtual machines or runtime engines)

gigue

🕺 Interpretation loop and JIT code generator to benchmark RISC-V isolation mechanisms

mitos

:film_strip: Python-based lexer and parser generator from an EBNF grammar.

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

pmpoke

👉 ASM tests around the PMP unit

sdvc

🍞 Simplified DiVinE Compiler to a custom ISA

sdvu

💻 Simple DiVinE custom ISA processing unit

womc

🇨 undergraduate C project for teachers

jitdomain-tests

Assembly tests following the JITDomain instruction-level domain isolation principle

opensmalltalk-vm

This is the VM used by Pharo

bloggy

📚 Sources for my blog https://qducasse.github.io

chimi

🏭 Chisel implementation of simple RIMI verifications

foundry

🔨 Base for an ACM/IEEE article

MiniBowser

💻 Mini browser performing HTTP requests and displaying site content

pharo-llvmDisassembler

Pharo bindings to the LLVM disassembler

pharo-unicorn

Pharo bindings to the Unicorn machine code simulation library

QDucasse

QDucasse.github.io

Sources of my blog https://qducasse.github.io

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC - adding JITDomain instructions

riscv-tools

RISC-V Tools (ISA Simulator and Tests)

rocket-chip

Rocket Chip Generator

rocket-tools

Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)

Ropper

Display information about files in different file formats and find gadgets to build rop chains for different architectures (x86/x86_64, ARM/ARM64, MIPS, PowerPC, SPARC64). For disassembly ropper uses the awesome Capstone Framework.

sdve-beem-benchmark

📈 BEEM Benchmark translation for Simple DiVinE

sdvs

⚙️ Simple DiVinE binary execution simulator

smol

👶 small lexer/parser/ast over a toy language

spike-lib

📙 Extension of Spike as a library with a simple API

SpikeRISCVSimulator

🚨 Pharo bindings to the Spike RISC-V simulator

unicorn

Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, X86)