混沌陣列's repositories
Smart-Internet-of-Thing-Alarm
基于STM32F103C8T_MCU的物联网智能闹钟，在V1.0测试版本当中，实现OLED屏幕显示和无线WiFi连接还有蓝牙通信，同时能够通过LM75芯片实现环境温度数据采集。
e203_hbirdv2
The Ultra-Low Power RISC-V Core
FPGAVerilogHDL
The Repository focused on developing the FPGA based on Verilog Hardware Device Language.
lenet5_hls
FPGA Accelerator for CNN using Vivado HLS
fpga-rocket-chip
Wrapper for Rocket-Chip on FPGAs
riscv-v-spec
Working draft of the proposed RISC-V V vector extension
vivado-risc-v
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
XiangShan
Open-source high-performance RISC-V processor
ara
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 0.10, working as a coprocessor to CORE-V's CVA6 core
asio
Boost.org asio module
bnn-fpga
Binarized Convolutional Neural Networks on Software-Programmable FPGAs
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
cocotb
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
cppzmq
Header-only C++ binding for libzmq
cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
docs
OpenHarmony documentation | OpenHarmony开发者文档
finn
Dataflow compiler for QNN inference on FPGAs
finn-hlslib
Vivado HLS library for FINN
Image-processing-algorithm
paper implement
json
JSON for Modern C++
mmdeploy
OpenMMLab Model Deployment Framework
picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
picorv32_Xilinx
A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
PipeCNN
An OpenCL-based FPGA Accelerator for Convolutional Neural Networks
ppl.nn
A primitive library for neural network
SEASKY_K210
K210 PCB YOLO
Vitis_HLS_Libraries
Vitis Libraries
yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard