Giters
ProjectDimlight
/
XinYiProcessor
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8
Watchers:
6
Issues:
13
Forks:
0
ProjectDimlight/XinYiProcessor Issues
FU: CP0 unit test
Closed
3 years ago
FU: WB unit test
Closed
3 years ago
Interruption will not occur in delay slot, be aware and needs further consideration
Closed
3 years ago
Performance Evaluation: where to handle multiple exception
Closed
3 years ago
TODO: ASID's machine behavior in CP0
Closed
3 years ago
Errors when compiling verilog modules using verilator
Closed
3 years ago
CP0 Cause.IP(7,2) should be wires directly from input interrupts, not regs
Closed
3 years ago
Comments count
1
Performance Evaluation: how to add in-branch-delay-slot signal
Closed
3 years ago
Deal with debug_interface
Closed
3 years ago
Add support for time interrupt
Closed
3 years ago
Put INT in FU stage, `flush` signal in WB
Closed
3 years ago
Comments count
2
FU: WB add exception before normal instruction
Closed
3 years ago
Comments count
1
CP0: exception after mtc0 WAW
Closed
3 years ago
Comments count
1