PritomP25's repositories
Adanced-Computer-System
A public repository for showcasing code written for ECSE 6320: Advanced Computer Systems
RISCV-Multicycle-Processor
A multi-cycle processor of a cpu designed according to the instruction set (assembly language) of RISC-V using System Verilog HDL.
Language:SystemVerilog000
RISCV-Pipelined-Processor-with-Hazard-Unit
An SystemVerilog implementation of a RISCV pipelined processor. The processor features a 5-stage pipeline architecture with integrated hazard detection and forwarding units to handle data and control hazards effectively.
Language:SystemVerilog000