Poulami2515 / Verilog

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Verilog

Component Instantiation : Providing instance of lower level module in higher level code
edge triggering : circuit is activated through transition portion of clock
            positive edge triggering : activation at rising edge
            negative edge triggering : activation at falling edge
level triggering : circuit is activated via voltage level

TRUTH TABLE OF D FLIP FLOP:

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generate statement : generate replication of hardware, provided in generate statement
              declaration of parameters, local parameters,
              input, output, inout ports, and specify blocks are prohibitted
begin-end block : sequential execution of statements
fork-join : parallel execution of statements

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