PavelZX / Kryon

FPGA,Verilog,Python

Kryon

FPGA Image Process, Connected Component Analysis-Labeling

This repository contains some verilog codes for Image Process, like image filtering, image smoothing, edge detecting, binary image erosion, dilation, RGB to HSI convertion and Connected Component Analysis-Labeling. The codes are detail commented, read the comments and you will know how to use it.

The Connected Component Analysis-Labeling algorithm here is a FPGA based parallel, pipelined, real time Algorithm. It only need to buffer one line of image data, no DDR needed.

I have writen two articles about these codes, it's in 中文，but google translate is goood enough.

• FPGA Image Processing basic skills - FPGA图像处理基本技巧

• Connected Component Analysis-Labeling algorithm upgrade - FPGA实现的连通域识别算法升级

"CCAL.py" is the source code of the Connected Component Labeling algorithm animation that I made:

• https://youtu.be/UVAxT60HppI
• 连通域识别算法动画演示

"C#"里的"加水印"是一个可以批量给图片文件加很多水印的小软件

"FPGA Ethernet Mac.py" is a FPGA MAC and a simple GUI written in python use MyHDL. It can run on ALINX黑金 AX516 Dev Board. PC can receive Raw Video transmited from FPGA through GBE.

My Photo Album: www.eyeem.com/becomequantum

Email: [e-mail]

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