PLC2 / PSI-vivadoIP_power_sink

Toggle FFs, SRLs and BRAMs to drain power for testing purposes

General Information

Maintainer

Jonas Purtschert [[e-mail]]

Author

Oliver Bründler [[e-mail]]

License

This library is published under PSI HDL Library License, which is LGPL plus some additional exceptions to clarify the LGPL terms in the context of firmware development.

Detailed Documentation

For details, refer to the Datasheet

Changelog

See Changelog

Dependencies

The required folder structure looks as given below (folder names must be matched exactly).

Alternatively the repository psi_fpga_all can be used. This repo contains all FPGA related repositories as submodules in the correct folder structure.

• TCL
  • PsiSim (2.1.0 or higher, for development only)
  • PsiIpPackage (2.0.0, for development only )
• VHDL
  • psi_common (2.5.0 or higher)
  • psi_tb (2.2.2 or higher, for development only)
• VivadoIp
  • vivadoIP_power_sink

Dependencies can also be checked out using the python script scripts/dependencies.py. For details, refer to the help of the script:

python dependencies.py -help

Note that the dependencies package must be installed in order to run the script.

Description

This IP-core allows toggline a configurable number of FFs, SRLs and BRAMs to drain power for testing purposes.

There is no simulation as the behavior is not easy to test in simulations (the most important thing is that nothing gets optimized away...).