OzuYatamutsu / Niu32-multicycle

A Verilog implementation of the Niu32 ISA, targeted for the Altera Cyclone II FPGA.

Niu32-multicycle processor

What is this?

This is a hardware implementation of the Niu32 instruction set. It specifies a bus-based architecture - i.e. a simple architecture with multiple cycles per instruction - and is written in Verilog, targeting the Altera Cyclone II FPGA board.

The project files included assume the use of Altera's Quartus II IDE. Open the project by opening the included Niu32_multicycle.qpf in Quartus II.

Processor states

FETCH+DECODE

FETCH1

FETCH2

FETCH3 (DECODE)

EX