Hazard is a Mips-Compatible RISC-CPU. It supports classical 5-level pipeline and supports Interrupt/Exception function.
Hazard is implemented by Verilog HDL.
This is a logisim simulation project for 5-level pipeline RISC-CPU.This version had implemented forwarding mechanism.
Hazard is a Mips-Compatible RISC-CPU. It supports classical 5-level pipeline and supports Interrupt/Exception function.
Hazard is implemented by Verilog HDL.
This is a logisim simulation project for 5-level pipeline RISC-CPU.This version had implemented forwarding mechanism.