Solution to make FIR elaboration faster

[Yangyu Chen]

Before start

• I have read the RISC-V ISA Manual.
• I have read the XiangShan Documents.
• I have searched the previous issues and did not find anything relevant.
• I have reviewed the commit messages from the relevant commit history.

Is your feature request related to a problem? Please describe.

The elaboration time after the new backend merged is too long, which makes RTL development not Minjie (agile).

For example, make verilog NUM_CORES=2 MFC=1 on commit c5beab3 takes less than 2 minutes to finish, but on commit aab8ef9 takes 36 minutes on my local machine with Intel 13900K.

After profiling the RTL elaboration, the bottleneck is the massive use of XSBundle. It needs to consume cde parameter to construct many things since it has HasXSParameter trait, which will take a lot of time for every XSBundle instance.

Describe the solution you'd like

A solution is to reduce the number of parameters in XSBundle to not derived from the HasXSParameter trait. We should no longer do a massive calculation in a trait for the cde parameter; we should calculate it when constructing cde parameters or add some parameter that the instance of this module may need and pass the result object to these instances.