OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

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DCacheTest failed

SpinEch0 opened this issue · comments

Describe the bug

Hi I write a DCache Module Test case. It failed with below message:

========== in test ==========
Assertion failed
    at WritebackQueue.scala:532 assert(!RegNext(!s_data_merge && !s_data_override))

I am sure s_data_merge and s_data_override are not both 0.
Maybe RegNext should be removed or with an initial value ?

assert(!(!s_data_merge && !s_data_override))  // it is ok!

To Reproduce

DCacheTest is a module with fake tilelink manager and a dcache, test code:

class DCacheBasicTest extends AnyFlatSpec with ChiselScalatestTester {
  behavior of "DCache"
  it should ("run") in {
    val defaultConfig = (new DefaultConfig)
    implicit val config = defaultConfig.alterPartial({
      case XSCoreParamsKey => defaultConfig(XSTileKey).head.copy()
    })
    println("========== Test the correctness of syntactic and datapath ==========")

    val dcache = LazyModule(new DCacheTest())

    test(dcache.module) { c =>
      println("========== in test ==========")
      // s0
      c.io.hartId.poke(0.U)
      c.io.l2_pf_store_only.poke(0.B)
      c.io.lqEmpty.poke(1.B)
      c.io.force_write.poke(0.B)
      println("cycle 0!!!!!!!!!!!!!!!!!!")
      c.clock.step(1)
      println("cycle 1!!!!!!!!!!!!!!!!!!")
      // c.clock.step()
    }
    println("========== end test ==========")
  }

Expected behavior

test success.

Screenshots

========== in test ==========
Assertion failed
    at WritebackQueue.scala:532 assert(!RegNext(!s_data_merge && !s_data_override))
Assertion failed
    at WritebackQueue.scala:532 assert(!RegNext(!s_data_merge && !s_data_override))
Assertion failed
    at MissQueue.scala:1010 assert(RegNext(PopCount(secondary_ready_vec) <= 1.U))
Assertion failed
    at MissQueue.scala:683 assert(RegNext(PopCount(Seq(io.primary_ready, io.secondary_ready, io.secondary_reject)) <= 1.U))
Assertion failed: depth should not be zero
    at PrefetcherMonitor.scala:152 assert(depth =/= 0.U, "depth should not be zero")

Environment (optional, if necessary):

OS: Ubuntu 20.04 LTS

Please provide more information, such as the details of your testcase.

By the way, I kindly remind you that you SHOULDN'T remove the issue template. Please always fill the issue template when opening an issue.

PrefetcherMonitor.scala:152 assert(depth =/= 0.U, "depth should not be zero") depth is not initiated