How Load Operations Perform Register Indirect Addressing

[Zihui Guo]

Hello. I would like to inquire about how XS handles the value of rs1 during load operations (such as LW, LBU, etc.).

For instance, is the address calculated as rs1 + imm, rs1[7:0] + imm, or in some other way?

When calculating the address for a load operation, is the value in the rs1 register truncated in any way? Or is the complete value of rs1used for the calculation?

Thank you very much, I look forward to your response.

[Tang Haojin]

Please refer to the ISA manual. XiangShan would not truncate the operand in any way for a load instruction. If the address is insane, an exception will be raised.

[Zihui Guo]

Please refer to the ISA manual. XiangShan would not truncate the operand in any way for a load instruction. If the address is insane, an exception will be raised.

Hi @Tang-Haojin . Thank you very much. I will close this issue and open a new one regarding the behavior I observed in XiangShan, which confuses me.

[Zihui Guo]

Hi @Tang-Haojin , I would like to ask how XiangShan handles situations where the immediate field of a load instruction exceeds the limits set by the instruction format?

[Tang Haojin]

This question is not related to XiangShan. Qualified compiler or programmer should know how to handle this.

For instance, say ld a0, imm(a1), if imm is inadequate for you to address the offset, you can change the value in a1.

[Tang Haojin]

Actually, many operations in RISC-V which cannot be completed in a single instruction can be divided into multiple instructions, like li a0, 0xf0000000_ffffffff. Hope this can help you.

[Zihui Guo]

Thank you for your detailed explanation! If the imm field exceeds the immediate number range of the instruction format, should it trigger an illegal instruction exception?

[Tang Haojin]

Please read the ISA spec first. Such instruction does not exist.

[Zihui Guo]

Thank you, I will give an example.
For example, the immediate format for the c.fld instruction is 5 bits. If I execute c.fld fa1, 128(a1), 128 exceeds the maximum value that can be represented by a 5-bit range.
How does Xiangshan handle this situation?

[Easton Man]

Hello, your assembly will most likely be rejected by any RISC-V compiler.

Please stop using XiangShan issue as a replacement for GPT/Google, please.

[Tang Haojin]

You may try

echo 'ld a0, 2047(a1)' | riscv64-linux-gnu-as -o a.out && riscv64-linux-gnu-objdump -S a.out

and

echo 'ld a0, 2048(a1)' | riscv64-linux-gnu-as -o a.out && riscv64-linux-gnu-objdump -S a.out

[Zihui Guo]

Thank you for your kind reminder. I didn't ask GPT/Google, but I observed some differences in behavior between XS and Spike, so I came to ask.

[Zihui Guo]

Thank you very much for your timely response. I will start a new issue to discuss the inconsistent behavior I encountered in more detail.