OpenXiangShan / XiangShan

Open-source high-performance RISC-V processor

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TileLink to CHI

changekkk opened this issue · comments

你好,想问一下,咱们目前昆明湖的设计中,总线协议是片内采用TileLink,片外采用CHI协议吗,之前说昆明湖准备替换TileLink为CHI,目前看到TL转CHI的bridge开发,这样的话,核间核内是保留了Tilelink协议然后通过Bridge,外设总线采用CHI的方案吗?

[TRANSLATION] Hello, I'd like to inquire about the current design of Kunminghu. Is the on-chip communication protocol TileLink, and the off-chip protocol CHI? Previously, it was mentioned that Kunminghuwas planning to replace TileLink with CHI. Currently, there seems to be development on the TL to CHI bridge. In this case, is the TileLink protocol retained for communication between cores internally, using a bridge, while the external peripheral bus adopts the CHI protocol?

昆明湖目前的设计是都采用 TileLink 协议,包括 L1-L2 和 L2-L3 之间的通信
我们未来的目标是 L1-L2 采用 TileLink,L2 向下为 CHI 协议的接口,连接 CHI L3/片上网络

[TRANSLATION] The current design of Kunminghu adopts TileLink in both L1-L2 and L2-L3 communication.
Our future goal is that L1-L2 uses TileLink, and L2 exposes a CHI interface, connecting to CHI L3/NOC

好的,目前昆明湖的核外总线,还是AXI4吗,还是CHI
[TRANSLATION] OK, currently, is the off-chip bus for Kunming Lake still AXI4, or has it transitioned to CHI?

目前核外的总线是 AXI4

[TRANSLATION] The current external protocol is AXI4