RTL Design and Implementation of High Performance Algorithm Logic Units
Efficient and accurate implementations of elementary functions, such as reciprocal and square root, are required in a wide range of applications. Designers have to carefully choose the best suited algorithms among numerous available techniques for custom implementations of these elementary functions that meet their design requirements, such as throughput, latency, and area. This project first explores the design trade-offs for alternative high-performance implementations of x−1, x0.5 and x−0.5 using several multiplicative techniques. Various trade-offs at the algorithmic and architectural levels are considered, such as the convergence rate of the algorithm, accuracy, inherent parallelism, resource requirements, throughput, and latency. We then utilize approximations of these three elementary functions over a normalized input x ∈ [1, 2) to approximate their values for x with an arbitrary precision in both fixed-point and floating-point formats. All the designs are verified against their synthesizable Verilog descriptions. We present the characteristics and implementation results of various elementary functions’ datapaths targeting a Xilinx Virtex-7 field-programmable gate array (FPGA).