OctCarp / SUSTech_CS202-Organization_2023s_Project-CPU

(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.

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SUSTech_CS202-Organization_2023s_Project-CPU

Single Cycle CPU: Our Project of CS202 2023 Spring: Computer Organization, SUSTech.

We use FPGA MINISYS 1-A to implement part of the MIPS32 instruction set. Support simple bit operations and binary addition, subtraction, multiplication, and division functions.

Final score: 121/100.

Project Information

You can check docs folder to see project requirement. And our project report in Chinese.

Repo Structure

├─ASM_Minisys-1A
├─CPU_Verilog
├─docs
├─EDA_Xilinx
└─unused
  • ASM_Minisys-1A : MIPS assembly file and binary file ,check Readme in this folder for more information.
  • CPU_Verilog : Verilog file for this project.
  • docs : Project requirement and our report.
  • EDA_Xilinx : Some files for Xilinx EDA Vivado, check Readme in this folder for more information.
  • unused : Some unused files, including Verilog file for onlinejudge test.

Quick Start

Use Vivado, select the device xc7a100tfgg484-1.

You can load bitstream file directly, or:

  1. Add the IP core in EDA_Xilinx/
  2. The RAM and ROM IP core loads the .coe file in EDA_Xilinx/ respectively
  3. Add the Verilog file in CPU_Verilog/
  4. Add the pin constraint file
  5. Use VIvado to simulate, synthesize, and then generate bitstream files

Board information

MINISYS

For example, if you want to do scene 1 test case 001:

  1. Press Program Restart Button
  2. Press UART Start Reprogram Button, then use UART to transmit sc1_new_version.txt
  3. Press Program Restart Button again to start the new program
  4. Let "Test case ID Input" low 3 bits switch be 001 (1 means on), then press Input confirm button
  5. Let Binary Value Input low 8 bits be the number 1 you want to input, then press Input confirm button, the Binary Value Input display will show the number 1 in high 8 bits.
  6. Let Binary Value Input low 8 bits be the number 2 you want to input, then press Input confirm button, the Binary Value Input display will show the number 2 in low 8 bits.
  7. Press Input confirm button, then the led or keyboard will show the result.

About

(Verilog+MIPS+FPGA MINISYS) (121/100): Single Cycle CPU: Our project of CS202 2023 Spring: Computer Organization, SUSTech. Taught by Prof. Jin ZHANG.

License:MIT License


Languages

Language:SystemVerilog 62.9%Language:Assembly 20.3%Language:Verilog 9.8%Language:Tcl 7.1%