NingHeChuan

xuanwu9000

design for yourself soc

Silicon_Peasant

automatic-verilog

automatic-verilog based on vimscript

IC_Linux_Config

ic

ninghechuan.github.io

bigwatermelon

合成大西瓜源码,修改版

MyBlog_Pic

Communication_Design

Open-FPGA

Devotes to open source FPGA

SpinalHDL

SpinalHDL core

iverilog

Icarus Verilog

wujian100_open

IC design and development should be faster，simpler and more reliable

Digital_Front_End_Verilog

homebrew-install

homebrew安装使用中科大镜像

e200_opensource

The Ultra-Low Power RISC Core

wavedrom.github.io

Digital timing diagram editor

MATLAB

logoly

A Pornhub Flavour Logo Generator

SpinalWorkshop

Labs to learn SpinalHDL

verilog_emacsauto.vim

verilog filetype plugin to enable emacs verilog-mode autos

visual_comm

an interactive visualisation of some basic concepts in wireless communication

Arty-Z7

Board repository for the Arty Z7