NewGamezzz / HW-Syn-Lab

⚙Hardware Synthesis Laboratory Using Verilog

Hardware Synthesis Laboratory

ROM

module rom(
    output reg [7:0] data,
    input wire [7:0] addr,
    input wire clk
    );
    
parameter width = 8;
parameter bits = 5;

reg [width-1:0] rom [2**bits-1:0];
initial $readmemb("rom.data", rom);

always@(posedge clk)
begin
    data <= rom[addr];
end
endmodule