Netnod

FPGA_NTP_SERVER

A FPGA implementation of the NTP and NTS protocols

robust-tjanst

nts-poc-python

NTS proof of concept in Python

base45

Specification of base45 encoding

md5

MD5 core written in Verilog

vadarklockan

A libray for securely getting time at boot.

go-cidrman

golang CIDR block management utilities

rosc_entropy

Ring oscillator core written in Verilog. Forked from https://git.cryptech.is/rng/rosc_entropy.git/

cmac

CMAC core written in verilog

keymem

Key memory core written in Verilog. Used by the FPGA_NTP_SERVER project

verilog-ethernet

Verilog Ethernet components for FPGA implementation

aes

AES core written in Verilog. Forked from https://git.cryptech.is/cipher/aes.git/

aes-siv

AES-SIV core written in Verilog

api_extension

api_extension core written in Verilog. Used by the FPGA_NTP_SERVER project

ipsec_exporter

Prometheus exporter for IPsec metrics.

nts

NTS core written in Verilog. This is just a core, see the FPGA_NTP_SERVER project for a complete implementation of the NTS protocol in a FPGA.

nts_noncegen

Nonce generator core written in Verilog

sha1

SHA1 core written in Verilog. Forked from https://git.cryptech.is/hash/sha1.git/

siphash

SIPHASH core written in Verilog

createtables

Creation of tables for IDNA

alice-lg

Alice - Through the Looking Glass https://lg-beta.de-cix.net https://lg.ecix.net

client_python

Prometheus instrumentation library for Python applications

cpython

A modified version of Python with support for the SSL_export_keying_material function. This function is neccesary to be able to implement the NTS protocol in Python.

draft-faltstrom-unicode12

Source for the draft-faltstrom-unicode11 internet draft

libaes_siv

An RFC5297-compliant C implementation of AES-SIV

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

netbox

IP address management (IPAM) and data center infrastructure management (DCIM) tool.

nixieclock-NCS314

Enhanced software for the GRA & AFCH NIXIE tube clock

openvpn-status

Parse OpenVPN status logs in Python

verilog-i2c

Verilog I2C interface for FPGA implementation